The present invention pertains to a microprocessor and a complex logic circuit utilizing the BiCMOS technology.
Heretofore, the BiCMOS technology has been applied widely to high speed SRAMs and gate arrays, and has proved to have excellent properties of high speed operation and low power consumption. With the recent remarkable advancements in the performance of RISC and CISC processors, it is predicted that, by the middle of 1990s, more advanced microprocessors capable of operating at 100 or more MIPS will be available. Because it will be crucial for microprocessors of the future to be provided with a built-in large capacity cache memory and, likewise, an FPU which require several million order integration of transistors on a chip, it is most preferable to employ BiCMOS technology which is capable of satisfying the fast operation, higher density integration and lower power consumption.
Such a prior art microprocessor utilizing the BiCMOS technology has been described in the IEEE, J. of SOLID STATE CIRCUITS Vo. 23, No. 2 April 1988, pp 500-506.
In a microprocessor, super multi inputs static logic circuits are frequently used. However, they are composed of CMOS gates or latch circuits having, at most, three to four inputs, therefore, there arise such problems as follows in the implementation of an extra high speed, high density integration microprocessor operating in excess of 100 MHz.
1) In proportion to an increase in the number of inputs, the number of logical stages increases, thereby increasing path delay, which proves to be a large hindrance to high speed operation. PA0 2) The increased number of logic gates results in an increased area of device regions. PA0 3) An increased number of interconnecting wiring required for connecting between the above logic gates increases a chip size. PA0 4) An increased number of logic circuits increases power consumption.